1. Field of the Invention
The present invention relates to a stacked semiconductor device in which semiconductor packages are stacked, and a printed circuit board including the stacked semiconductor device.
2. Description of the Related Art
In recent years, along with the sophistication and miniaturization of electronic devices, demands have been growing for sophisticated and miniaturized electronic components and semiconductor devices used in the electronic devices. A semiconductor package called “ball grid array (BGA)” is known as the structure for realizing a high-pin count and compact semiconductor device. For further miniaturization, a stacked semiconductor device called “package-on-package (PoP)” is known, in which a semiconductor package including a memory semiconductor element is stacked on a semiconductor package including a logic semiconductor element, for example.
The stacked semiconductor device is advantageous in that, even when the number of electrode terminals is increased, the ratio of a mounting area can be reduced by stacking the semiconductor packages, that is, the miniaturization is possible. The stacking of the semiconductor packages is suitable for high-speed transmission because a signal wiring distance is reduced as compared with the planar arrangement. The stacked semiconductor device therefore tends to be employed in electronic devices more often in the future. On the other hand, the operating frequency of the semiconductor element is becoming higher in order to support high-speed operation of the electronic devices.
Achieving signal operation of the semiconductor element at a high frequency such as several hundreds of MHz or more requires improving high frequency characteristics of a power source for supplying power to the semiconductor element to stabilize the potential at the operating frequency. To achieve this, a power supply wiring of a printed wiring board needs to have low inductance in a corresponding operating frequency region.
As a conventional method for decreasing the inductance of the power supply wiring of the printed wiring board, Japanese Patent Application Laid-Open No. 2009-182087 describes that a power supply wiring and a ground wiring are arranged in adjacent to each other or that multiple wirings are provided. In Japanese Patent Application Laid-Open No. 2009-182087, wiring layers are connected by connection conductors, and a power supply connection conductor and a ground connection conductor are arranged in adjacent to each other, to thereby increase the mutual inductance. Further, multiple power supply connection conductors and multiple ground connection conductors are arranged, to thereby decrease the self-inductance. As a result, the combined inductance of the power supply wiring and the ground wiring obtained by subtracting the mutual inductance from the self-inductance is decreased.
However, the technology described in Japanese Patent Application Laid-Open No. 2009-182087 is not always sufficient for further decreasing the inductance.
In a general stacked semiconductor device, a power supply wiring for supplying power to both a first semiconductor element located in a lower stage and a second semiconductor element located in an upper stage is formed in a lower first printed wiring board, and the power is supplied from a mother board. Because the first semiconductor element is to be mounted on the first printed wiring board, a connection portion of the first printed wiring board to an upper second printed wiring board needs to be provided at a position that avoids the first semiconductor element. In this case, in the first printed wiring board, an interval between connection lands for the second printed wiring board and an interval between connection lands for the mother board are not always equal to each other. Similarly, the position of the connection land for the second printed wiring board and the position of the connection land for the mother board when projected from above are not always identical to each other. Thus, a path of the power supply wiring that connects a first surface layer and a second surface layer of the first printed wiring board is bent. The bent power supply wiring may be responsible for an increase in self-inductance of the power supply wiring.
It is often the case that the printed wiring board for use in the stacked semiconductor device is made up of a core layer and a build-up layer. In the case of a printed wiring board in which a via of the build-up layer is connected immediately above a via of the core layer, the yields are low and the cost is high. It is therefore necessary to offset the position of the via that connects the build-up layers and the position of the via that connects the core layers. Thus, a path of the power supply wiring is bent, which may similarly be responsible for an increase in self-inductance.
On the other hand, a conceivable method for decreasing the self-inductance of the power supply wiring for supplying power to the second semiconductor element is to increase the number of power supply lands of the first printed wiring board on the mother board side so as to increase the number of power supply paths. In this configuration, however, it is difficult to take out a signal wiring of a surface layer of the mother board on which the stacked semiconductor device is mounted.